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T4240 IFC timing too long

Question asked by blanchard daniel on Dec 7, 2018
Latest reply on Dec 17, 2018 by blanchard daniel

Hello, we are using a SRAM connected to a T4240 via the IFC Chip Select 1 in GPCM mode.
We computed that a write to this RAM should last about 65ns,
We measured that, in fact, the write access lasts 98ns.

 

Could you please give us hints to explain these additional 33ns (and, even better, how to get rid of them) ?

 

Thanks by advance.

 

Best Regards,

 

Daniel Blanchard

 

The processor is configured as follows :

 

T4240, SYSCLK = 66.66MHz,  1667MHz
DDR_CLK = 933MHz (1866.66MT/s)
IP_CLK = 366MHz
IFC_CLOCK = 92MHz

 

IFC configuration :

 

IFC:CCR = 0x03008000
- CLKDIV = 0x3 (Clock division ratio divide by 4)
- CLK_DLY = 0x0 (IFC clock NO delay)
- INV_CLK_EN = 0x1 (IFC clock is inverted)

 

IFC:AMASK_CS[1] = 0xFF800000 (8MBytes)

 

IFC:FTIM0_CS[1] = 0x00020001
- TACSE = 0x0 (reserved, @ end to CS enable, min : 0x1 : 1 IFC module input clock)
- TEADC = 0x2 (2 IFC module input clocks)
- TEAHC = 0x1 (1 IFC module input clock)

 

IFC:FTIM1_CS[1] = 0x04001900
- TACO = 0x4 (4 IFC module input clocks)
- TRAD = 0x19 (25 IFC module input clocks)

 

IFC:FTIM2_CS[1] = 0x0308000F
- TCS = 0x3 (3 IFC module input clocks)
- TCH = 0x2 (2 IFC module input clocks)
- TWP = 0xF (15 IFC module input clocks)

 

IFC:FTIM3_CS[1] = 0x0
- TAAD : 0 (reserved, GPCM address access delay in burst mode, min : 0x1 : 1 IFC module input clock)

 

IFC:CSPR_CS[1] : 0x----0185
- BA = __SRAM (Base address)
- PS = 0x3 (Port size : 32-bits)
- WP = 0x0 (R/W allowed
- MSEL = 0x2 (GPMC)
- V = 0x1 (Bank is valid)

 

Nota : With TACSE = TAAD = 0x1 (minimum values), the cycle time increases of 1 clock

 

Test program, bare metal code, interrupts masked :
    cmplw    r31, r30
    bf     0, 0x48F0
    stw    r29, 0(r31)
    addi    r31, r31, 4
    addi    r29, r29, 1
    b    0x48D8

 

Corresponding chronogram :

Yellow : CS

Green : ALE

Blue : One Data bus bit

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