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IMX6DL EIM CONFIG

Question asked by Paul Kail on Dec 4, 2018
Latest reply on Dec 7, 2018 by igorpadykov

I set the external pins to AD0-AD15 (address line) and D0-D7 (data line). 

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this is gpio config information:

MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

 

 

MX6DL_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0,
MX6DL_PAD_CSI0_VSYNC__WEIM_WEIM_D_1,
MX6DL_PAD_CSI0_DAT4__WEIM_WEIM_D_2,
MX6DL_PAD_CSI0_DAT5__WEIM_WEIM_D_3,
MX6DL_PAD_CSI0_DAT6__WEIM_WEIM_D_4,
MX6DL_PAD_CSI0_DAT7__WEIM_WEIM_D_5,
MX6DL_PAD_CSI0_DAT8__WEIM_WEIM_D_6,
MX6DL_PAD_CSI0_DAT9__WEIM_WEIM_D_7,

////////////////////////////////////////////////////////////////////////////

this is eim config regs information:

regs[CS0GCR1] = 0x01040081;
regs[CS0GCR2] = 0x00000001;
regs[CS0RCR1] = 0xC000000;
regs[CS0RCR2] = 0x0;
regs[CS0WCR1] = 0xA000000;

 

I operated EIM and found that the address line action was wrong.

The following is a waveform of the read address 0x1:

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