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DDR4 CK_A and CK_B Functionality

Question asked by Alistair Schofield on Dec 4, 2018
Latest reply on Dec 5, 2018 by Yuri Muhin



I'm currently designing a module using the i.MX8MQ and I am in the middle of creating a schematic using 4 Micron DDR4 x8 memory chips. I'm slightly apprehensive about the usage of CK_T/C_A and CK_T/C_B. I was just wondering how these clocks should be connected to the 4 independent DDR4 chips? I (quite possibly naively) think that CK_A should run to bytes 0 and 1 of the DDR4 and that CK_B should run to bytes 2 and 3 because the LPDDR4 used on the reference design sort of implies that is the case. Can someone confirm this is correct for me? I've also tried to find something more explicit in the hardware design guide but have been unable to do so.


Thanks for any help in advance.