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SCTimer: Can't clear HALT bit while leaving STOP bit set

Question asked by David Rick on Dec 3, 2018
Latest reply on Dec 5, 2018 by jeremyzhou

I am programming the SCTimer on an LPCxpresso 54102 development board. Most of my code uses SDK calls, but the driver was missing the capability to "arm" the SCT from software and subsequently "trigger" it from hardware. To accomplish this, one needs to clear the HALT bit in the SCT CTRL register, but leave the STOP bit set. Normally, clearing HALT will also clear STOP, but UM10850 Chapter 15 states:

HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is
possible to remove the halt condition while keeping the SCT in the stop condition
(not running) with a single write to this register to simultaneously clear the HALT bit
and set the STOP bit.

Therefore, I augmented the SDK driver with the following additional function:

inline void SCTIMER_ArmTimer(SCT_Type *base, sctimer_counter_t countertoArm)
/*!
* @brief Clears HALT bit but keeps timer stopped by setting STOP bit
*
* This allows counting to be started by an external input
*/

{
    uint32_t temp;

    /* Set STOP and Clear HALT */

    /* use L side if operating in 32-bit mode or user wants to start L counter */
    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoArm == kSCTIMER_Counter_L))
    {
     /* Docs say update of HALT and STOP must occur simultaneously */
     temp = base->CTRL;
        temp |= (SCT_CTRL_STOP_L_MASK);       
     temp &= ~(SCT_CTRL_HALT_L_MASK);
     base->CTRL = temp;          
    }
    else  /* arm the H counter */
    {
     /* Docs say update of HALT and STOP must occur simultaneously */
     temp = base->CTRL;
        temp |= (SCT_CTRL_STOP_H_MASK);
        temp &= ~(SCT_CTRL_HALT_H_MASK);
     base->CTRL = temp;          
    }
}

Contrary to what's stated in the manual, this does not result in the STOP bit staying set. Instead, STOP gets cleared and the SCT begins counting. I can add a second write to CTRL that sets the STOP bit, but by then the SCT is already has started counting and is in the wrong state. 

 

What is the correct way to implement this "arm"..."trigger" functionality?

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