Spi slave mode problem

[mauroscoccia]

Good evening,

I have communication problem with the spi bus on IMX6 processor.
My goal is to configure a spi line of the IMX6 processor in slave mode.
From the tests carried out by me, this configuration only works if the number of bytes to be sent to the slave line is equal to 8.
In this case the test involves sending to the slave line a pattern of 8 bytes so preset:
byte 1 = 1
bytes 2 = 2
byte 3 = 3
bytes 4 = 4
byte 5 = 5
bytes 6 = 6
bytes 7 = 7
bytes 7 = 8
The data received on the slave side correspond to those mentioned above.
The registers slave side are configured as follows:
CONREG register value is 3f03001 slave
CONFIGREG register value is f00055 slave

In the second case with a number of bytes to be sent (from spi master device  to spi imx6 slave device) is to equal to 16 with the following pattern,
byte 1 = 1
bytes 2 = 2
byte 3 = 3
bytes 4 = 4
byte 5 = 5
bytes 6 = 6
bytes 7 = 7
bytes 8 = 8
byte 9 = 9
bytes 10 = 10
bytes 11 = 11
byte 12 = 12
bytes 13 = 13
byte 14 = 14
byte 15 = 15
bytes 16 = 16
The result obtained on the slave side (first run)  is as follows:
o_rx_data1 of 0 is 0
o_rx_data1 of 1 is 0
o_rx_data1 of 2 is 0
o_rx_data1 of 3 is 0
o_rx_data1 of 4 is 0
o_rx_data1 of 5 is 2c
o_rx_data1 of 6 is 3
o_rx_data1 of 7 is ff
o_rx_data1 of 8 is 1
o_rx_data1 of 9 is 2
o_rx_data1 of 10 is 3
o_rx_data1 of 11 is 4
o_rx_data1 of 12 is 5
o_rx_data1 of 13 is 6
o_rx_data1 of 14 is 7
o_rx_data1 of 15 is 8

The registers are configured as follows:
CONREG register value is 7f03001 slave
CONFIGREG register value is f00055 slave

The result obtained on the slave side (at second run first run)  is as follows:

o_rx_data1 of 0 is 9
o_rx_data1 of 1 is 10
o_rx_data1 of 2 is 11
o_rx_data1 of 3 is 12
o_rx_data1 of 4 is 13
o_rx_data1 of 5 is 14
o_rx_data1 of 6 is 15
o_rx_data1 of 7 is 16
o_rx_data1 of 8 is 1
o_rx_data1 of 9 is 2
o_rx_data1 of 10 is 3
o_rx_data1 of 11 is 4
o_rx_data1 of 12 is 5
o_rx_data1 of 13 is 6
o_rx_data1 of 14 is 7
o_rx_data1 of 15 is 8

The registers are configured as follows:
CONREG register value is 7f03001 slave
CONFIGREG register value is f00055 slave

Attached there are also two paint files where the signals of the spi lines are recorded, both in the positive and in the negative case.
Thank you for your cooperation,

I greet you cordially.

[mauroscoccia]

Hello Igor.

First of all thank you for your support

I forgot to mention that I'm not using linux OS , but rather Pike OS, and so i can not use the patch.

Regarding the first hardware limitation that you mention, the data buffer used in the test (16 bytes) does not fill the TX_FIFO.

Thank you for your cooperation,

I greet you cordially.

[igorpadykov]

Hi mauro

one can check latest patches:

[PATCH RFC 0/5] *** SPI Slave mode support *** 

The last patch 5/5 says:

http://lists.infradead.org/pipermail/linux-arm-kernel/2017-April/501267.html 

"Following HW limitation applies:
1. ECSPI has a HW issue when works in Slave mode, after 64
words written to TXFIFO, even TXFIFO becomes empty,
ECSPI_TXDATA keeps shift out the last word data,
so we have to disable ECSPI when in slave mode after the
transfer completes
2. Due to Freescale errata ERR003775 "eCSPI: Burst completion by Chip
Select (SS) signal in Slave mode is not functional" burst size must
be set exactly to the size of the transfer. This limit SPI transaction
with maximum 2^12 bits."

As for ecspi slave support in nxp linux releases:

https://community.nxp.com/message/966323 

Best regards
igor
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