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T1042 - DDR Controller Commad Signal Timings

Question asked by Embedded Engineer on Nov 28, 2018
Latest reply on Nov 29, 2018 by ufedor

Hi, We are trying to bringup DDR3L discrete RAMs on our custom board. We modified our RCW to set DDR clock frequency to 533MHz. We created a default QCVS DDR3 validation project and ran validation tests. All tests are failing by giving following errors:


Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware


We verified signal routing, CLK, CKE and checked signals on probes on all command signals (RAS, CAS, WE, BA, Address etc.) used during DRAM init. However, we noticed two following abnormalities in the signals:


1.  CKE was following init sequence but once it goes high it does not come to low (although CKE_PLS bits are set to use 4 clocks)

2.  Command signals (we tested RAS and CAS) are being asserted for 3~4 clock cycles i.e 7~8 ns when running on 533MHz (although 1T timing is set in DDR controller settings). Please checkout the attached snapshot of RAS signal during init sequence.


Can someone confirm why T1042/DDR-controller is driving these signals with such behavior? Thanks.