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clock cycle activity for LPC1114

Question asked by Haohao Liao on Nov 27, 2018
Latest reply on Nov 29, 2018 by Haohao Liao

I am now working with the LPC1114 which utilizes the ARM CORTEX M0 architecture. I have one question about the instruction set summary of the ARMv6M Thumb instruction set. I want to know what the processor does during each single clock cycle for each instruction. For example, if I have the following code where I want to write something to the GPIO0DATA register to change the level of the IO output (Actually toggle PIO0_3) 
loop 
LDR R0, =(0x50003FFC); GPIO0DATA Base + 0x3FFC, address 0x5000 3FFC 
LDR R1, [R0]; 
MOVS R2, #(1<<3); 
; Store the value of R1 into GPIO0DATA 
EORS R1, R1, R2; 
STR R1, [R0]; 
B loop 
Question 1: 
Let's say the first clock cycle is when the chip fetches the LDR R0, =(0x50003FFC) instruction.  what the chip does in the following clock cycles? Also if there is any reference that could explain it, that will be really helpful. 

 

Question 2: 
I find that the time between PIO0_3 is toggled every 15 cycles. However, based on the instruction set summary, it should be 11 cycles (LDR/STR takes two cycles and MOVS, EORS takes 1 cycle, B takes 3 cycles), anyone knows why? If there is a timing diagram to explain it, that would be great! 

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