The datasheet for the PCIE reference clock input specifies a max cycle to cycle jitter of 35ps.
The hardware developers guide indicates using the IDT 9FGV0241 will work in this application
However, this datasheet's maximum cycle to cycle jitter is specified at 50ps
35ps seems like a pretty tight spec based on looking at some other PCIe parts, so I assume it has been specified because something breaks when jitter gets beyond that.
What happens to the PCIe link if the jitter spec is violated (how was that spec determined)?