Hello, we use DDR3L device from Micron for our memory plane of a T1042 design. The memory uses DQ0 and DQ8 (x16 device) as the prime DQ for the write levelling feature.
Does the T1042 DDR memory controller expects the prime DQ to be connected to MDQ0/MDQ8/... for the write levelling process to work ? OR does it monitor all DQs (within a byte)
The DDR3 controller has DDR_DDR_DQ_MAP registers to re-route DQ (so is my understanding). Does this process take place "in front" of the write levelling engine (I guess so).
Thanks for the clarification