Hi Sir,
We need to control SPI device via SPI1. However, it does not work well (the CLK always keeps in low). Do you have any ideas about that? I can see these SPI nodes by ls -al /sys/class/spidev/ command as below:
root@imx8qxpmek:~# ls -al /sys/class/spidev/
drwxr-xr-x 2 root root 0 Oct 3 05:44 .
drwxr-xr-x 63 root root 0 Oct 3 05:44 ..
lrwxrwxrwx 1 root root 0 Oct 3 05:44 spidev32763.0 -> ../../devices/platform/5a030000.lpspi/spi_master/spi32763/spi32763.0/spidev/spidev32763.0
lrwxrwxrwx 1 root root 0 Oct 3 05:44 spidev32764.0 -> ../../devices/platform/5a020000.lpspi/spi_master/spi32764/spi32764.0/spidev/spidev32764.0
lrwxrwxrwx 1 root root 0 Oct 3 05:44 spidev32765.0 -> ../../devices/platform/5a010000.lpspi/spi_master/spi32765/spi32765.0/spidev/spidev32765.0
lrwxrwxrwx 1 root root 0 Oct 3 05:44 spidev32766.0 -> ../../devices/platform/5a000000.lpspi/spi_master/spi32766/spi32766.0/spidev/spidev32766.0
root@imx8qxpmek:~#
Below is what I configured in dts and dtsi files.
.dts file:
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
SC_P_SAI0_TXFS_ADMA_SPI1_SCK 0xD600004c
SC_P_SAI0_TXD_ADMA_SPI1_SDO 0xD600004c
SC_P_SAI0_TXC_ADMA_SPI1_SDI 0xD600004c
// SC_P_SAI0_RXD_ADMA_SPI1_CS0 0xD600004c
>;
};
pinctrl_lpspi1_cs: lpspi1cs {
fsl,pins = <
SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0xE0000021
>;
};
......
&lpspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
status = "okay";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
dtsi file:
lpspi1: lpspi@5a010000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x0 0x5a010000 0x0 0x10000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QXP_SPI1_CLK>,
<&clk IMX8QXP_SPI1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_SPI1_CLK>;
assigned-clock-rates = <20000000>;
power-domains = <&pd_dma_lpspi1>;
status = "disabled";
};
Best regards
Kevin
Hi Kevin,
Previously there is a typo in CLK driver, please check following changes is added:
clk-imx8qxp.c
clks[IMX8QXP_SPI1_CLK] = imx_clk_gate_scu("spi1_clk", "spi1_div", SC_R_SPI_2, SC_PM_CLK_PER, (void __iomem *)(LPSPI_1_LPCG), 0, 0);
change to :
clks[IMX8QXP_SPI1_CLK] = imx_clk_gate_scu("spi1_clk", "spi1_div", SC_R_SPI_1, SC_PM_CLK_PER, (void __iomem *)(LPSPI_1_LPCG), 0, 0);
Best regards,
Danwei