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RGMII ping fails at U-boot T1022

Question asked by RAM MURMU on Nov 26, 2018
Latest reply on Dec 6, 2018 by Pavel Chubakov

We have a custom board based on T1022 processor, in the board there are two PHY [DP83867] connected to processor via RGMII port. When we ping the server from uboot then the FCS error is being reported in the tx packets using T32 debugging cable.

The "mii info" displays the two phys attached to the processor but ping is not working at uboot. Is this somekind of configuration error or configuration related to RGMII is missing?

 

U-BOOT log

---------------------------------------------------------------------------------------------------------------------------------------------------------------

Initializing....using SPD
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
2 GiB left unmapped
Loading second stage boot loader .................................................................................................

U-Boot 2016.012.0+ga9b437f (Nov 19 2018 - 05:41:10 +0530)

CPU0: T1022E, Version: 1.1, (0x85290211)
Core: e5500, Version: 2.1, (0x80241021)
Single Source Clock Configuration
Clock Configuration:
CPU0:1400 MHz, CPU1:1400 MHz,
CCB:600 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:150 MHz
QE:300 MHz
FMAN1: 600 MHz
QMAN: 300 MHz
PME: 300 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c10000e 0e000000 00000000 00000000
00000010: 40000000 00400012 ec110000 21000000
00000020: 00000000 00000000 00000000 00038000
00000030: 00000000 c0165a05 00000000 00000000
I2C: ready
Board: T1022D4RDB
SPI: ready
DRAM: Detected UDIMM 76.XXXXX.XXX0B
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
4 GiB (DDR4, 64-bit, CL=11, ECC on)
L2: 256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 64 (0x40)
SEC0: RNG instantiated
NAND: 1024 MiB
MMC: FSL_SDHC: 0
PLL read error 1
CCXK: Configure PLL FAILED
CCXK::PHY out of reset
SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB
PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, no link, regs @ 0xfe250000
PCIe2: Bus 01 - 01
PCIe3: disabled
PCIe4: disabled
In: serial
Out: serial
Err: serial
SERDES Reference : 0x40
Net: Initializing Fman
SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB
Fman1: Uploading microcode version 106.4.18
Could not get PHY for FSL_MDIO0: addr 0 2
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0 2
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0 7
Failed to connect
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 [PRIME]
Hit any key to stop autoboot: 0
=> mii info
PHY 0x01: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX
PHY 0x04: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX
=> ping $serverip
FM1@DTSEC5 Waiting for PHY auto negotiation to complete......... TIMEOUT !
FM1@DTSEC5: No link.
Using FM1@DTSEC1 device

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