I'm working with the P1021. The Reference Manual states that if CCSR space is used, then it should be marked as cache-inhibited and guard.
How do I mark this address space, or any other address space as cache-inhibited and guarded?
Corresponding MMU TLB has to have I and G bits set - please refer to the PowerPC™ e500 Core Family Reference Manual, 12.3.6 TLB Entry Field Definitions:
Thank you sir.
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