I have some questions about MPIC programming the MPIC in the T1040 platform.
xIDR behavior : Let's say that EIDR is set to 0x0 (disable all cores targets) , ff the interrupt is triggered, is the activity bit in EIVPR register set ??
Multicast interrupts with int destination : Let's take Global Timers interrupts as example.
From the section 25.4.6 :
""" Note that when global timer interrupts are set to multicast (interrupt more that one
processor by setting more than 1 Pn bit in the GTDRxn), each recipient processor must
acknowledge, take delivery and EOI that interrupt. That is, the interrupt is delivered to
each processor as a unique copy. """
What's happening if only one core reads the interrupt ? does the interrupt remains in activity (A bit of xIVPR register remains set until all targetted cores finishes the interrupt handling by writing the EOI register) ?