AnsweredAssumed Answered

Actual hardware ECC algorithm and configuration used in i.MX28 application processor

Question asked by Bertha Brot on Nov 20, 2018
Latest reply on Nov 21, 2018 by Bertha Brot

Hello NXP Community,

 

can anybody tell me what actual error correcting code algorithm, parameters, and possibly other magic ingredients are used in i.MX28 application processors to calculate ECCs for NAND memory?

 

I have a NAND dump of an embedded device using a MCIMX283DVM4B. If my understanding of the i.MX28 Applications Processor Reference Manual regarding the firmware configuration block (FCB) is correct, my specific target device uses the following configuration:

page data size = 2048 bytes

total page size = 2112 bytes

sectors per block = 64

ECC block N = 4 (BCH8)

ECC block N size = 512 bytes

ECC block 0 = 4 (BCH8)

ECC block 0 size = 512 bytes

 

Up to now, I was not able to correctly calculate any of the BCH ECCs contained in my NAND dump using typical polynoms (e.g. 0x201B) and reversing bits of data bytes for any corresponding block which is a show stopper for my intended data recovery.

 

During my Internet research concerning hardware-generated ECCs for NAND memory, I stumbled upon some similar asked questions and threads, some of them several years old, like NAND Flash - encoding data with hardware ECC unit - generator polynomial , but nowhere enough information, or also appreciated source code, was provided to solve my actual problem.

 

I really hope that somebody can help me to correctly calculate and use the BCH error correcting codes for data recovery purposes regarding my i.MX28-based device.

Outcomes