I have a T2080 board ,which communicates with 10G ethernet PHY via the SERDES1 lane0,lane1,lane2,lane3 with XAUI protocol, the each lane should work at 3.125G .
I configure the Serdes protocol in RCW as following:
SRDS_PLL_REF_CLK_SEL_S1 0b1 125/156.25MHz
the serdes1 pll1 reference clock is 156.25M Hz. but the the serdes1PLL1 is not lock and the RST_DONE bit is NOT DONE and RST_ERR bit is ERROR.
the rest PLL can lock correctly.