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SERDES1 x4 XAUI protocol, the each lane work at 3.125G,PLL1 NOT LOCK

Question asked by xing shen on Nov 20, 2018
Latest reply on Nov 21, 2018 by ufedor

Hi,

   I have a T2080 board ,which communicates with 10G ethernet PHY via the SERDES1 lane0,lane1,lane2,lane3 with XAUI protocol, the each lane should work at 3.125G .

I configure the Serdes protocol in RCW as following:

SERDES_PRTCL_1 0x51
SERDES_PRTCL_2 0x36

SRDS_PLL_REF_CLK_SEL_S1 0b1 125/156.25MHz

the serdes1 pll1 reference clock is 156.25M Hz. but the the serdes1PLL1 is not lock and the RST_DONE bit is NOT DONE and RST_ERR bit is ERROR.

the rest PLL can lock correctly.

 

Best regards

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