When I boot T4240QDS for SMP mode, it sometimes(1/10) happen L3 error(CPC1_CPCERDET=0x60). my boot step is below:
1. core0 boot up successfully and L2/L3 both off
2. core0 configure spin table (cache inhibit ) and boot page
3. core0 reset secondary cores and secondary cores enter spin loop successfully
4. core0 enable L2/L3 with error check (CPCCSR0=0xc0000000, CPCERRINTEN=0)
5. core0 setup secondary cores spintable->addr
6. secondary cores exit spin loop and goto their spintable->addr, SMP successfully.
However, sometimes, some one of secondary cores will randomly fail by a machine check event. I attached with CodeWariorr could see that CPC1_CPCERDET=0x60 and the failed core happened machine check(MCSSR0=0x23e034, MCSRR1=0x30)
If without CPC error check (CPCCSR0=0x80000000) at step 4 will not reproduce it
If enable CPC before reseting secondary cores, i.e. switch step 3 and 4, will not reproduce it
a. CPCERRINTEN=0, even happen CPC error, why it will cause machine check?
b. I see in uboot core0 firstly enable L2/L3 then reset secondary core, Is this the only correct flow?