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MCG/PLL Configuration

Question asked by Brian Mohlman on Nov 16, 2018
Latest reply on Nov 20, 2018 by Brian Mohlman



I am using a KV46 in my design and have the MCG setup to run in PEE mode. I am using an external 8MHz xtal for clocking and I have the PLL setup so that the 8MHZ is /1 coming in. from there I have the vdiv set to 25 so that the PLL is clocking @200MHz feeding into the MCG clock. From the diagram in the reference manual there is no /2 block prior to running into the multiplexer of the MCGoutclk, but in the clock configurator software and indeed in the code it looks like it does get divided by 2. So the clock going into the output divider is 100MHz. For the outdiv1, outdiv2 ,and outdiv4 I have set to /1, /2, /4 respectively to get 100 MHz system clock, 50 MHz fast peripheral clock, and 25 flash memory clock. It appears to run fine with no issue. The manual excerpt from chapter 6 on clocking says, "The MCG has a PLL that provides a multiplying function on the input clock source to generate PLL clock frequencies from 110 MHz to 240 MHz and to generate PLL 2x clock frequencies from 220 MHz to 480 MHz". When I try to set the registers up through the MCUXpresso clock configurator tool to match the software driver I have, it shows errors that the PLL clock must be  set between 220MHz and 480MHz. So I am wondering is my setup not correct, even though it appears to run fine and the peripheral clock that feeds SPI, CAN, & I2C seems to work correctly. Any clarity on how I should be setting the  PLL up?