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LS1021A IFC Interface Aborts During Read

Question asked by Charles Yocum on Nov 14, 2018
Latest reply on Nov 19, 2018 by Charles Yocum

I am working on a custom LS1021A board. We are currently booting U-Boot and Linux from flash on IFC CS0 with no issues. We are attempting to set up an FPGA on CS1 and expose a section of memory to the ARM processor using the IFC bus. Here's the U-Boot configuration:

/* ARRIA */
#define CONFIG_SYS_ARRIA_BASE   0x7c000000
#define ARRIA_BASE_PHYS         CONFIG_SYS_ARRIA_BASE

#define CONFIG_SYS_ARRIA_CSPR_EXT       (0x0)
#define CONFIG_SYS_ARRIA_CSPR       (CSPR_PHYS_ADDR(ARRIA_BASE_PHYS) | \
                                        CSPR_PORT_SIZE_16 | \
                                        CSPR_MSEL_GPCM | \
                                        CSPR_V)
#define CONFIG_SYS_ARRIA_AMASK          IFC_AMASK(32 * 1024 * 1024)
#define CONFIG_SYS_ARRIA_CSOR       (CSOR_GPCM_ADM_SHIFT(4) | \
                                        CSOR_GPCM_GPMODE_ASIC | \
                                        CSOR_GPCM_GPTO(256) | \
                                        CSOR_GPCM_GAPERRD(1) | \
                                        CSOR_GPCM_TRHZ_20)
#define CONFIG_SYS_ARRIA_FTIM0      (FTIM0_GPCM_TACSE(0x1) | \
                                        FTIM0_GPCM_TEADC(0x1) | \
                                        FTIM0_GPCM_TEAHC(0xff))
#define CONFIG_SYS_ARRIA_FTIM1      (FTIM1_GPCM_TACO(0x1) | \
                                        FTIM1_GPCM_TRAD(0x21))
#define CONFIG_SYS_ARRIA_FTIM2      (FTIM2_GPCM_TCS(0x1) | \
                                        FTIM2_GPCM_TCH(0x1) | \
                                        FTIM2_GPCM_TWP(0x21))
#define CONFIG_SYS_ARRIA_FTIM3      FTIM3_NAND_TWW(0x3)
#define CONFIG_SYS_CSPR1_EXT        CONFIG_SYS_ARRIA_CSPR_EXT
#define CONFIG_SYS_CSPR1            CONFIG_SYS_ARRIA_CSPR
#define CONFIG_SYS_AMASK1           CONFIG_SYS_ARRIA_AMASK
#define CONFIG_SYS_CSOR1            CONFIG_SYS_ARRIA_CSOR
#define CONFIG_SYS_CS1_FTIM0        CONFIG_SYS_ARRIA_FTIM0
#define CONFIG_SYS_CS1_FTIM1        CONFIG_SYS_ARRIA_FTIM1
#define CONFIG_SYS_CS1_FTIM2        CONFIG_SYS_ARRIA_FTIM2
#define CONFIG_SYS_CS1_FTIM3        CONFIG_SYS_ARRIA_FTIM3

On the FPGA side of things, everything looks perfect, exactly as detailed in Section 23.7.2 of the LS1021ARM reference manual. In Linux, the write appears to work, but the read generates the following:

Nov 12 19:56:04 ls1021atwr user.alert kernel: Unhandled fault: synchronous external abort (0x1210) at 0x76ff6080
Nov 12 19:56:04 ls1021atwr user.alert kernel: pgd = be565900
Nov 12 19:56:04 ls1021atwr user.alert kernel: [76ff6080] *pgd=bd6a0003, *pmd=bd671003, *pte=56000007c000fc3

I've been writing 0xfeedface to 0x7c000080, but using an address in the space generates a similar error. Is there a misconfigured signal on the IFC interface that could be generating this type of abort?

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