AnsweredAssumed Answered

The DDR SDRAM timing configuration 4 register (TIMING_CFG_4)

Question asked by yansong zhu on Nov 14, 2018
Latest reply on Nov 18, 2018 by Bulat Karymov

I can't understand the function of RWT which is a part of TIMING_CFG_4.


"Read-to-write turnaround for same chip select
Specifies how many cycles are added between a read to write turnaround for transactions to the same
chip select. If a value of 0000 is chosen, then the DDR controller uses the value used for transactions to
different chip selects, as defined in TIMING_CFG_0[RWT]. This field can be used to improve performance
when operating in burst-chop mode by forcing transactions to the same chip select to use extra cycles,
while transaction to different chip selects can utilize the tri-state time on the DRAM interface. Regardless
of the value that is set in this field, the value defined by TIMING_CFG_0[RWT] also is met before issuing a
write command."


How this field used to improve performance when operating in burst-chop mode?