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LS1021A-TWR won't enable new Chip Select

Question asked by William Banning on Nov 12, 2018
Latest reply on Nov 13, 2018 by Charles Yocum

We're developing a custom board based on the LS1021A-TWR. It has an Arria 5 GZ FPGA is attached to the ARM processor's IFC bus and we are currently trying to enable Chip Select 3 to interface with the FPGA using Generic ASIC protocol.  We're u-booting from NOR Flash and I've added the following to our ls1021atwr.h file for our configuration:


#define CONFIG_SYS_FPGA_FLASH2 0x70000000
#define CONFIG_SYS_CSPR3_EXT (0x0)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_FLASH2) | \
                                                                                        CSPR_PORT_SIZE_16 | \
                                                                                        CSPR_MSEL_GPCM | \
                                                                                        CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(32 * 1024 * 1024)
#define CONFIG_SYS_CSOR3 (CSOR_NOR_ADM_SHIFT(4) | \
                                                     CSOR_GPCM_GPMODE_ASIC | \
                                                     CSOR_GPCM_GPTO(256) | \
                                                     CSOR_GPCM_GAPERRD(1) | \
                                                     CSOR_GPCM_TRHZ_20)

#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x1) | \
                                                            FTIM0_GPCM_TEADC(0x01) | \
                                                            FTIM0_GPCM_TEAHC(0xff))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x01) | \
                                                            FTIM1_GPCM_TRAD(0x21))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x01) | \
                                                            FTIM2_GPCM_TCH(0x1) | \
                                                            FTIM2_GPCM_TWP(0x21))
#define CONFIG_SYS_CS3_FTIM3 FTIM3_NAND_TWW(0x3)

 

I'm successfully running u-boot, however, when I try to read or write to 0x70000000 the u-boot session crashes.  We've probed the Chip Select lines and see that Chip Select 0 is always active and that Chip Select 3 never goes active.  From what I know about the LS1021A, the processor itself should be handling the switch between chip selects, but it seems like Chip Select 3 never gets activated.  Is there something else I need to do to properly set up Chip Select 3 or enable the switching between chip selects?

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