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iMX7 M4 LMEM DDR Caching

Question asked by ALLEN BLAYLOCK on Nov 11, 2018
Latest reply on Nov 30, 2018 by Yuri Muhin
Branched to a new discussion

I have found a few different threads discussing the M4 cache controller:


JTAG debugger not working with enabled LMEM cache on M4 Core(iMX7) 

i.MX7D: atomic compare and swap instructions don't work with cache 

IMX7 M4 caching and execution speed 


The documentation on the controller is pretty sparse and a few of the threads indicate issues with the implementation of the cache controller. None of the reference material documents or scopes the issues which makes development particularly challenging. Would it be possible to get an improved list and scope of the issues in the LMEM cache controller?


I have experienced issues with the cache controller in the following areas:

  • The reference manual documents that 0x8000_0000 - 0x8020_0000 is cacheable
    • Experimentally I have found 0x8000_0000 - 0x8040_0000 cacheable BUT 0x8020_0000 - 0x8040_0000 has some sort of bug that causes memory/instruction corruption.
    • I have also experimentally found that 0x8000_0000 - 0x8080_0000 is affected by the LMEM controller in some way. Setting a memory region at 0x8040_0000 to have the instruction access disabled results in a IACCVIOL despite no executable code living at or above that address, only the heap was linked to the address. Perhaps the cache controller is reading it as though it were executable?
  • The Code Cache bus is doesn't provide any performance gain for "cacheable" DDR in the aliased 0x1000_0000 - 0x1FFE_FFFF memory range. There is no reference or documentation that the Code Cache bus is non-functional.


The biggest question I have at this point is:

Is there a workaround to the LMEM cache controller affecting the memory ranges 0x8020_0000 - 0x8080_0000? Or can a description of the issue be provided so I can understand what is and isn't safe from a code/data perspective.