VDD_CACHE_CAP ( Pad N12 ) in i.MX6 Duallite

[markwilliams]

Could this be confirmed please? I am working on a design that will support each processor variant. When it says the solo "can be NC" does it have to be? I originally placed a resistor link here but in practice getting that under centre of the processor is an issue! I would rather tie VDD_CACHE_CAP to VDDSOC_CAP for all processor variants.

[markwilliams]

Hi Yuri,

Is there any way we could find out if the cache cap pin can be left connected to VDD_HIGH_CAP for Solo? Pin N12 is in the centre of the BGA and the bottom layer is covered in decoupling to meet the stringent cap requirements. Adding a footprint for a link resistor would involve routing VDD_CACHE_CAP out of the BGA (0.125mm track) to a resistor then back in to VDD_HIGH_CAP.

If I have to do this for common hardware design is that ok? It would be much easier if VDD_CACHE_CAP could remain connected.

Mark

[Yuri]

Hello,

  Table 2-14 (Miscellaneous recommendations) of the recent Hardware Development Guide for i.MX6 states, that: “NC contacts are no connect and must be left unconnected. Depending on the feature set, some versions of the IC may have NC contacts connected inside the BGA.” Note, this statement was definitely updated regarding previous releases of the Guide, according to the recent Guide revision history (updated row 5 of table Table 2-14).

http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf 

Have a great day,
Yuri

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