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Re: VDD_CACHE_CAP ( Pad N12 ) in i.MX6 Duallite

Question asked by markwilliams on Sep 14, 2018
Latest reply on Feb 27, 2019 by markwilliams
Branched from an earlier discussion

Could this be confirmed please? I am working on a design that will support each processor variant. When it says the solo "can be NC" does it have to be? I originally placed a resistor link here but in practice getting that under centre of the processor is an issue! I would rather tie VDD_CACHE_CAP to VDDSOC_CAP for all processor variants.