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Core Clock divide

Question asked by Grzegorz Mikitiuk on Nov 10, 2018
Latest reply on Nov 12, 2018 by Robin_Shen

Hello,

 

I've got strange problem using SIM_CLKDIV1 to lower core clock on K80

 

I'm running PLL on this board and i want to be able to divide high PLL clocks to not exceed bus/core clocks limits.

 

The problem is if i use this:

SIM -> CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0)| //core
SIM_CLKDIV1_OUTDIV2(1)| // Busclk
SIM_CLKDIV1_OUTDIV3(3)| // FlexBus
SIM_CLKDIV1_OUTDIV4(7)); // Flash

It works, every clock is divided properly but if i try:

SIM -> CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(1)| //core
SIM_CLKDIV1_OUTDIV2(1)| // Busclk
SIM_CLKDIV1_OUTDIV3(3)| // FlexBus
SIM_CLKDIV1_OUTDIV4(7)); // Flash

Write is ignored and i end up with default values. Where is the catch? I read that maximum divide ratio between core and other clocks is 8 but i'm not exceeding this limitations

 

Thanks for any help

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