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imx.RT1060 can't work with hyperFlash?

Question asked by ranshalit on Oct 31, 2018
Latest reply on Nov 7, 2018 by CarlosCasillas

Hello,

 

We just got today a new mimxrt1060 EVK.

It works fine with ram debug, but on configuring to spiflash it fails as following:

 

Wed Oct 31, 2018 17:22:14: IAR Embedded Workbench 8.30.1 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armproc.dll)
Wed Oct 31, 2018 17:22:14: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\config\debugger\NXP\iMXRT.dmac
Wed Oct 31, 2018 17:22:14: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\config\debugger\NXP\iMXRT_Trace.dmac
Wed Oct 31, 2018 17:22:14: Loading the CMSIS-DAP driver
Wed Oct 31, 2018 17:22:14: Probe: CMSIS-DAP probe SW module ver 1.13
Wed Oct 31, 2018 17:22:14: Probe: CMSIS-DAP S/N '0229000005da88a000000000000000000000000097969905' mapped to a number 97969905.
Wed Oct 31, 2018 17:22:14: Emulation layer version 4.34
Wed Oct 31, 2018 17:22:15: Notification to init-after-power-up hookup.
Wed Oct 31, 2018 17:22:15: Notification to core-connect hookup.
Wed Oct 31, 2018 17:22:15: Connected DAP v1 on SWD. Detected IDCODE=0xbd11477.
Wed Oct 31, 2018 17:22:15: Probe: ConnectSpec='CMSIS-DAP:0229000005da88a000000000000000000000000097969905:7-3A81E2DE-0-0000'.
Wed Oct 31, 2018 17:22:15: Connecting to TAP#0 DAP AHB-AP port 0 (IDR=0x4770041).
Wed Oct 31, 2018 17:22:15: Recognized CPUID=0x411fc271 Cortex-M7 r1p1 arch ARMv7-M
Wed Oct 31, 2018 17:22:15: Set cacheable access on AHB-AP port 0 (HPROT=0xeb000000).
Wed Oct 31, 2018 17:22:15: Debug resources: 8 instruction comparators, 4 data watchpoints.
Wed Oct 31, 2018 17:22:15: MultiCore: Asynchronous core execution FORCED.
Wed Oct 31, 2018 17:22:15: MultiCore: Synchronous core execution DISABLED.
Wed Oct 31, 2018 17:22:15: LowLevelReset(hardware, delay 200)
Wed Oct 31, 2018 17:22:16: Notification to init-after-hw-reset hookup.
Wed Oct 31, 2018 17:22:16: Probe: ConnectSpec='CMSIS-DAP:0229000005da88a000000000000000000000000097969905:7-3A81E2DE-0-0000'.
Wed Oct 31, 2018 17:22:16: Connecting to TAP#0 DAP AHB-AP port 0 (IDR=0x4770041).
Wed Oct 31, 2018 17:22:16: Recognized CPUID=0x411fc271 Cortex-M7 r1p1 arch ARMv7-M
Wed Oct 31, 2018 17:22:16: Set cacheable access on AHB-AP port 0 (HPROT=0xeb000000).
Wed Oct 31, 2018 17:22:16: Debug resources: 8 instruction comparators, 4 data watchpoints.
Wed Oct 31, 2018 17:22:16: CPU status - IN RESET
Wed Oct 31, 2018 17:22:17: Loaded debugee: C:\Users\ransh\Downloads\SDK_2.4.0_EVK-MIMXRT1060 (3) (1)\boards\evkmimxrt1060\demo_apps\shell\iar\flexspi_nor_debug\shell.out
Wed Oct 31, 2018 17:22:17: Download error at 0x60000000: downloading into non-writable memory.
Wed Oct 31, 2018 17:22:17: Download error at 0x60001000: downloading into non-writable memory.
Wed Oct 31, 2018 17:22:17: Download error at 0x60002000: downloading into non-writable memory.
Wed Oct 31, 2018 17:22:17: Download error at 0x60002000: memory write failed.

 

* In ram debugging with IAR (same project , imxrt1060, sdk 2.4.0) - no issue. Only with spiflash debug in IAR.

* With mimxrt1050 (sdk 2.4.2) no issues in spinor debug with IAR.

* It seems that xip examples is for qspi (not hyperflash) .
   On trying to use the imxrt1050 hyperflash files instead of qspi, there is an error on startup !

* We also tried to change switch state - sw 7 by default is for qspi, we changed it to spiflash - 0110 - yet, no change in behaviour. Maybe it's SW5 ? Wwhy sw5 is not mentioned in MIMX1060 user guide ?

 

Can anyone help with this ?

 

ranran

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