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i.MX6SX drives MCLK for audio codec

Question asked by Seven Lin on Oct 31, 2018
Latest reply on Oct 31, 2018 by igorpadykov

Hi,

 

We want to use i.MX6SX to drive MCLK signal for our audio codec (that means our codec is i2s slave), we have configured in the dtsi file as below:


&ssi2 {
assigned-clocks = <&clks IMX6SX_CLK_PLL4>,
<&clks IMX6SX_PLL4_BYPASS>,
<&clks IMX6SX_CLK_SSI2_SEL>;
assigned-clock-parents = <&clks IMX6SX_CLK_OSC>,
<&clks IMX6SX_CLK_PLL4>,
<&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <737280000>, <0>, <0>;
status = "okay";
};


pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x13088
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x13088
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x12088
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x13088

 

and we also call clk_prepare_enable() in our audio machine driver to enable MCLK, then we could measure the signal by the oscilloscope.

 

We have some questions:
1. We could measure the MCLK signal from both cpu and codec, is it normal? why not the signal is only output from cpu?
2. How to change MCLK frequency? currently, we have measured MCLK frequency is 24 MHz, if we want to change to 12M, where we should modify?

 

 

Thanks.

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