I am using a rev. 3.1 MPC8347. I have a 4MB dual-ported SRAM chip (IDT70T35) on LCS1 and and another 4 MB dual-ported SRAM chip (IDT70T35) on LCS3. Both are configured to use UPMs.
My problem is that if I write something (byte, half-word, word, etc..) with the MPC8347 e300 in the lower half (first 2MB) of any of these chips memory mapped areas (as per my ORx/BRx settings), it also shows up in the lower memory map of the other chip (i.e. the intended write worked, but it also "wrote to the other chip" at the same chip offset). What is strange is that if I write something in the upper half of any of these chips, the write is done correctly in that it only shows up in the chip I intended to write (as per my ORx/BRx settings)??!?!
I have checked all my ORx, BRx, LBLAWBARx amd LBLAWARx settings ad nauseum for overlap. Everything seems fine. I have even verified with a scope as to whether the chip select lines going to these two IDT70T35 chips are being activated properly by the MPC8347. Yup, everything checks out.
This seems to suggest that the local bus mirroring is happening within the MPC8347 somehow?!?!
Has anyone had a similar problem? If so, could you possibly help me out with this MPC8347 mystery?