Memory addresses in MPU

[er_arpit_arora]

Hello NXP, I have a question regarding the memory addresses in the Hello World demo for IMX RT 1060 processor. I see the following code in board.c.

What I am failing to understand from all the documentation on the Arm website for Cortex M7 and NXP is where do the addresses specified in the code below come from.

Could someone point me to the correct resource online which can help me here?

/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);

/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

/* Region 2 setting */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
#else
/* Setting Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB);
#endif

/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);

/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);

/* The define sets the cacheable memory to shareable,
* this suggestion is referred from chapter 2.2.1 Memory regions,
* types and attributes in Cortex-M7 Devices, Generic User Guide */
#if defined(SDRAM_IS_SHAREABLE)
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#else
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#endif

/* Region 9 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
* accessed by cache can be put here */
/* Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(9, 0x81E00000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);

[Takashi_Kashiwagi]

Hi Arora,

> What I am failing to understand from all the documentation on the Arm website for Cortex M7 and NXP is where do the

> addresses specified in the code below come from.

> Could someone point me to the correct resource online which can help me here?

The address specified by the MPU and its attributes are designed by the board designer. In other words, you can design it freely.

Since I could not find a good comment site on MPU, I will describe the basic things as follows.

Sorry, I found it.....

https://www.nxp.com/docs/en/application-note/AN12042.pdf

First of all, you need to understand which address each device is mapped from CPU reference manual and board design document. (Internal ROM / RAM, External ROM / RAM, pheriphral registers, etc)

Next, you set appropriate attributes for each address (Executability of the program, shared access validity/invalid, cache validity/invalid, etc.).

Regarding the attribute, most of the time it is set as follows.
1. In the area where the program is executed, specify the executable attribute.
2. Please enable caching if you want to improve performance.
3. Enable shared access and turn off caching in areas other than CPU (DMA etc) that may be accessed.
4. In areas where you want to keep the order of memory access, disable shared access and caching.

Setting this attribute is very important. Setting inappropriate attributes will degrade CPU performance or cause memory faults.

[In Japanese]

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MPUで指定されているアドレスとその属性は、ボードの設計者が設計します。つまりあなたは自由にそれを設計できます。

MPUについての良い解説サイトが見当たらなかったので基本的なことを以下の通り記載します。

ごめん、ありました。

まず、あなたはCPUのリファレンスマニュアルとボードの設計書から各Deviceがどのaddressにマッピングされているかを理解する必要があります。（Internal ROM/RAM, External ROM/RAM, pheriphral registers, etc.）

次に、それぞれのアドレスに対して適切な属性を設定します（プログラムの実行可否、共有アクセスの有効無効、キャッシュの有効無効等）。

属性についてですが、たいていは以下のように設定します。
1. プログラムを実行するエリアは、実行可能の属性を指定してください。
2. パフォーマンスを上げたい場合はキャッシュを有効にしてください。
3. CPU以外（DMAなど）がアクセスする可能性のあるエリアは、共有アクセスを有効にし、キャッシュをOFFしてください。

4. メモリへのアクセス順番を守りたいエリアでは、共有アクセスとキャッシュを無効にします。

この属性の設定はとても重要です。不適切な属性を設定すると、CPUのパフォーマンスが低下したりメモリフォールトが発生します。

--

Best Regards,

T.Kashiwagi