Poptelecan Constantin

LPC1788 - TFT Image is Teared. Checked all timings. Help please.

Discussion created by Poptelecan Constantin on Oct 27, 2018
Latest reply on Nov 1, 2018 by Poptelecan Constantin

  Hello everyone. 

 

    I am banging my head with this for weeks now. I have a custom board, that sports a LPC1788 208 pin + AS4C8M16SA Alliance Memory 128M - 8M x 16 bit Synchronous DRAM + an TFT RFC570Y-6IW-DNN.

 

   One by one - I started with the memory. runs at 60 MhZ clock, checked all timings with an oscilloscope, checked the integrity with a simple code - writing and reading back from memory. All is fine. 

  

   I am using a simple routine with the LCD. Nothing fancy. No emwin. I simply want to display a slideshow of BMPs on it. But until then I want to draw a simple line. It's tearing the image in half. I will attach some pictures. I GUESS is a timing issue, but I cannot figure out what's the problem. Checked vsync / hsync with an oscilloscope (on the trace) - and looks fine. Checked the TFT clock - 6.3 MhZ looks fine. I checked every single trace with a multimeter under a microscope ... all fine. Checked the voltages, took care of screen orientation registers (mentioned in the datasheet) ... still cannot have a clear picture. I don't know what to do next really ... 

 

  This is the datasheet for the TFT...

    https://www.tme.eu/en/Document/aa5324e3d006c80d8ca67e400949ee5c/RFC570Y-6IW-DNN.pdf

 

 I don't understand the timing graphs , I used the values from the table at page 14. 

 

 The simple code that works somehow is here:

#include "LCD/lpc177x_8x_lcd.h"
#include "EX_SDRAM/EX_SDRAM.H"

#define C_GLCD_CLK_PER_LINE     (C_GLCD_H_SIZE + C_GLCD_H_PULSE + C_GLCD_H_FRONT_PORCH + C_GLCD_H_BACK_PORCH)
#define C_GLCD_LINES_PER_FRAME  (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
#define C_GLCD_PIX_CLK          (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME * C_GLCD_REFRESH_FREQ)
 
 //************************************************************************
void GLCD_Ctrl (Bool bEna)
{
 volatile uint32_t i;
  if (bEna)
  {
    LPC_LCD->CTRL |= (1<<0);
    for(i = C_GLCD_PWR_ENA_DIS_DLY; i; i--)
    LPC_LCD->CTRL |= (1<<11);
  }
  else
  {
    LPC_LCD->CTRL &= ~(1<<11);
    for(i = C_GLCD_PWR_ENA_DIS_DLY; i; i--);
    LPC_LCD->CTRL &= ~(1<<0);
  }
}
 
 //*************************************************************************/
void GLCD_Init (const unsigned long *pPain, const unsigned long * pPallete)
{
 unsigned long i,j;
 unsigned long *pDst = (unsigned long *)LCD_VRAM_BASE_ADDR;
 
  /* R */
  LPC_IOCON->P0_4  = 0x27;  // LCD_VD_0
  LPC_IOCON->P0_5   = 0x27;  // LCD_VD_1
  LPC_IOCON->P4_28   = 0x27;  // LCD_VD_2
  LPC_IOCON->P4_29  = 0x27;  // LCD_VD_3
  LPC_IOCON->P2_6   = 0x27;  // LCD_VD_4
  LPC_IOCON->P2_7   = 0x27;  // LCD_VD_5
  LPC_IOCON->P2_8   = 0x27;  // LCD_VD_6
  LPC_IOCON->P2_9  = 0x27;  // LCD_VD_7
  /* G */    
  LPC_IOCON->P0_6  = 0x27;  // LCD_VD_8
  LPC_IOCON->P0_7  = 0x27;  // LCD_VD_9
  LPC_IOCON->P1_20  = 0x27;  // LCD_VD_10
  LPC_IOCON->P1_21  = 0x27;  // LCD_VD_11
  LPC_IOCON->P1_22  = 0x27;  // LCD_VD_12
  LPC_IOCON->P1_23  = 0x27;  // LCD_VD_13
  LPC_IOCON->P1_24  = 0x27;  // LCD_VD_14
  LPC_IOCON->P1_25  = 0x27;  // LCD_VD_15
 /* B */
  LPC_IOCON->P0_8  = 0x27;  // LCD_VD_16
  LPC_IOCON->P0_9  = 0x27;  // LCD_VD_17
  LPC_IOCON->P2_12  = 0x27;  // LCD_VD_18
  LPC_IOCON->P2_13  = 0x27;  // LCD_VD_19
  LPC_IOCON->P1_26  = 0x27;  // LCD_VD_20
  LPC_IOCON->P1_27  = 0x27;  // LCD_VD_21
  LPC_IOCON->P1_28  = 0x27;  // LCD_VD_22
  LPC_IOCON->P1_29  = 0x27;  // LCD_VD_23
  LPC_IOCON->P2_2   = 0x27;  // LCD_DCLK
  LPC_IOCON->P2_5   = 0x27;  // LCD_LP -- HSYNC
  LPC_IOCON->P2_3   = 0x27;  // LCD_FP -- VSYNC
  LPC_IOCON->P2_4   = 0x27;  // LCD_ENAB_M -- LCDDEN
 
 //Turn on LCD clock
 LPC_SC->PCONP |= 1<<0;
  // Disable cursor
 LPC_LCD->CRSR_CTRL &=~(1<<0);
 // disable GLCD controller 
 LPC_LCD->CTRL = 0;
 
 LPC_LCD->CTRL &= ~(0x07 <<1);
 LPC_LCD->CTRL |= (5<<1);
 
 // TFT panel
 LPC_LCD->CTRL |= (1<<5);
 // single panel
 LPC_LCD->CTRL &= ~(1<<7);
 // notmal output
 LPC_LCD->CTRL |= (1<<8);
 // little endian byte order
 LPC_LCD->CTRL &= ~(1<<9);
 // little endian pix order
 LPC_LCD->CTRL &= ~(1<<10);
 // disable power
 LPC_LCD->CTRL &= ~(1<<11);
 // init pixel clock
 LPC_SC->LCD_CFG = PeripheralClock / ((unsigned long) C_GLCD_PIX_CLK);
 // bypass inrenal clk divider
 LPC_LCD->POL |=(1<<26);
 // clock source for the LCD block is HCLK
 LPC_LCD->POL &= ~(1<<5);
 // LCDFP pin is active LOW and inactive HIGH
 LPC_LCD->POL |= (1<<11);
 // LCDLP pin is active LOW and inactive HIGH
 LPC_LCD->POL |= (1<<12);
 // data is driven out into the LCD on the falling edge
 LPC_LCD->POL &= ~(1<<13);
 // active high
 LPC_LCD->POL &= ~(1<<14);
 LPC_LCD->POL &= ~(0x3FF <<16);
 LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
 
 // init Horizontal Timing
 LPC_LCD->TIMH = 0; //reset TIMH before set value
 LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
 LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
 LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
 LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
 
 // init Vertical Timing
 LPC_LCD->TIMV = 0;  //reset TIMV value before setting
 LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
 LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
 LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
 LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
 
 // Frame Base Address doubleword aligned
 LPC_LCD->UPBASE = LCD_VRAM_BASE_ADDR & ~7UL ;
 LPC_LCD->LPBASE = LCD_VRAM_BASE_ADDR & ~7UL ;
 
 
 //here I am trying to draw 2 red lines. WORKS but the second line continues to the 3rd part of the screen.
 
 for( i = 0; 320*5 > i; i++)
 {
  *pDst++ = 0xFF0000;
 }
 
 
 //here I am trying to draw from line 5 to line 100 - the colour green. Also works - but the last 2 lines are teared.
   for( i = 320*5; 320*100 > i; i++)
 {
    //*pDst16++ = purple;
  *pDst++ = 0x00FF00;
 }  
}
and the .h as follows:
#ifndef __LPC177X_8X_LCD_H_
#define __LPC177X_8X_LCD_H_

#include "LPC177x_8x.h"
#include "lpc_types.h"
#include "system_LPC177x_8x.h"
#define LCD_VRAM_BASE_ADDR  ((unsigned long)SDRAM_BASE + 0x00010000)
#define LCD_CURSOR_BASE_ADDR  ((unsigned long)0x20088800)
#define C_GLCD_REFRESH_FREQ     (30) // Hz
#define C_GLCD_H_SIZE           320
#define C_GLCD_H_PULSE          30 
#define C_GLCD_H_FRONT_PORCH    20
#define C_GLCD_H_BACK_PORCH     38 
#define C_GLCD_V_SIZE           240
#define C_GLCD_V_PULSE          3
#define C_GLCD_V_FRONT_PORCH    5 
#define C_GLCD_V_BACK_PORCH     15 
#define C_GLCD_PWR_ENA_DIS_DLY  1000
#define C_GLCD_ENA_DIS_DLY      1000
#define TEXT_DEF_TAB_SIZE 5
#define TEXT_BEL1_FUNC()
void GLCD_Init (const unsigned long *pPain, const unsigned long * pPallete);
void GLCD_Ctrl (Bool bEna);
#endif   /*__LPC177X_8X_LCD_H_*/
Also checked against UM10470 all the lcd registers, added some , tweaked some ... but made no difference. 
Please point me to the right direction. 
In this configuration I am measuring on the trace with an oscilloscope the values: 
   LCD clock - 6.31 MhZ
   HSync - 15.4 Khz
   VSync - 58.8 Hz
 Thankyou verry much in advance !
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