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How to connect to imx6Ull with ddr_init.jlinkscript file?

Question asked by Kevin Cronn on Oct 25, 2018
Latest reply on Oct 26, 2018 by Kevin Cronn

I am using the IMX6ULL on the evkmcimx6ull eval board with a Segger J-link Plus debugger. The SDK_2.2_MCIM6ULL documentations says to run script ddr_init.jlinkscript on the command line when starting the GDB server.

 

From Getting Started with MCUXpresso SDK for i.MX 6ULL:

Since it is required to run the ddr_init.jlinkscript to initialize DDR before loading the example application, use
command window to run JLinkGDBServer with the -scriptfile option. Assuming the J-Link software is installed,
change to the directory that contains the software like “C:\Program Files (x86)\SEGGER\JLink_V614”, run the
command “ JLinkGDBServer -device MCIMX6Y2 -scriptfile “<install_dir>/boards/<board_name>/
<example_type>/<application_name>/ddr_init.jlinkscript”.

 

When I run this on the command line:

JLinkGDBServer.exe -device MCIMX6Y2 -scriptfile .\ddr_init.jlinkscript

 

I get this error:

SEGGER J-Link GDB Server V6.34h Command Line Version

JLinkARM.dll V6.34h (DLL compiled Oct 9 2018 15:48:11)

Command line: -device MCIMX6Y2 -scriptfile .\ddr_init.jlinkscript
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: off
Init regs on start: off
Silent mode: off
Single run mode: off
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: .\ddr_init.jlinkscript
J-Link settings file: none
------Target related settings------
Target device: MCIMX6Y2
Target interface: JTAG
Target interface speed: 4000kHz
Target endian: little

Connecting to J-Link...
J-Link is connected.
Firmware: J-Link V10 compiled Sep 4 2018 11:24:21
Hardware: V10.10
S/N: 600105098
Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
Checking target voltage...
Target voltage: 3.33 V
Listening on TCP/IP port 2331
Connecting to target...WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3
, NumBitsSet = 2)

WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

ERROR: Cortex-A/R-JTAG (connect): Could not determine address of core debug registers. Incorrect CoreSight ROM table in device?
ERROR: Could not connect to target.
Target connection failed. GDBServer will be closed...Restoring target state and closing J-Link connection...
Shutting down...
Could not connect to target.
Please check power, connection and settings.

 

If I run the same command without the script it connects ok, but of course the iMX6 is not set up to run. Does anyone know what the issue is with the script? Here is the contents of ddr_init.jlinkscript, given with the SDK:

/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. K.G. *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
**********************************************************************
----------------------------------------------------------------------
Purpose :
---------------------------END-OF-HEADER------------------------------
*/


void Clock_Init() {
// Enable all clocks
MEM_WriteU32(0x020c4068,0xffffffff);
MEM_WriteU32(0x020c406c,0xffffffff);
MEM_WriteU32(0x020c4070,0xffffffff);
MEM_WriteU32(0x020c4074,0xffffffff);
MEM_WriteU32(0x020c4078,0xffffffff);
MEM_WriteU32(0x020c407c,0xffffffff);
MEM_WriteU32(0x020c4080,0xffffffff);

Report("Clock Init Done");
}

void DDR_Init() {
// Config IOMUX for ddr
MEM_WriteU32(0x020E04B4,0x000C0000);
MEM_WriteU32(0x020E04AC,0x00000000);
MEM_WriteU32(0x020E027C,0x00000030);
MEM_WriteU32(0x020E0250,0x00000030);
MEM_WriteU32(0x020E024C,0x00000030);
MEM_WriteU32(0x020E0490,0x00000030);
MEM_WriteU32(0x020E0288,0x00000030);
MEM_WriteU32(0x020E0270,0x00000000);
MEM_WriteU32(0x020E0260,0x00000030);
MEM_WriteU32(0x020E0264,0x00000030);
MEM_WriteU32(0x020E04A0,0x00000030);
MEM_WriteU32(0x020E0494,0x00020000);
MEM_WriteU32(0x020E0280,0x00000030);
MEM_WriteU32(0x020E0284,0x00000030);
MEM_WriteU32(0x020E04B0,0x00020000);
MEM_WriteU32(0x020E0498,0x00000030);
MEM_WriteU32(0x020E04A4,0x00000030);
MEM_WriteU32(0x020E0244,0x00000030);
MEM_WriteU32(0x020E0248,0x00000030);

// Config DDR Controller Registers
MEM_WriteU32(0x021B001C,0x00008000);
MEM_WriteU32(0x021B0800,0xA1390003);
MEM_WriteU32(0x021B080C,0x00150019);
MEM_WriteU32(0x021B083C,0x41550153);
MEM_WriteU32(0x021B0848,0x40403A3E);
MEM_WriteU32(0x021B0850,0x40402F2A);
MEM_WriteU32(0x021B081C,0x33333333);
MEM_WriteU32(0x021B0820,0x33333333);
MEM_WriteU32(0x021B082C,0xf3333333);
MEM_WriteU32(0x021B0830,0xf3333333);
MEM_WriteU32(0x021B08C0,0x00944009);
MEM_WriteU32(0x021B08b8,0x00000800);

// Config MMDC init
MEM_WriteU32(0x021B0004,0x0002002D);
MEM_WriteU32(0x021B0008,0x1B333030);
MEM_WriteU32(0x021B000C,0x676B52F3);
MEM_WriteU32(0x021B0010,0xB66D0B63);
MEM_WriteU32(0x021B0014,0x01FF00DB);
MEM_WriteU32(0x021B0018,0x00201740);
MEM_WriteU32(0x021B001C,0x00008000);
MEM_WriteU32(0x021B002C,0x000026D2);
MEM_WriteU32(0x021B0030,0x006B1023);
MEM_WriteU32(0x021B0040,0x0000005F);
MEM_WriteU32(0x021B0000,0x85180000);
MEM_WriteU32(0x021B0890,0x00400000);
MEM_WriteU32(0x021B001C,0x02008032);
MEM_WriteU32(0x021B001C,0x00008033);
MEM_WriteU32(0x021B001C,0x00048031);
MEM_WriteU32(0x021B001C,0x15208030);
MEM_WriteU32(0x021B001C,0x04008040);
MEM_WriteU32(0x021B0020,0x00000800);
MEM_WriteU32(0x021B0818,0x00000227);
MEM_WriteU32(0x021B0004,0x0002552D);
MEM_WriteU32(0x021B0404,0x00011006);
MEM_WriteU32(0x021B001C,0x00000000);

Report("DDR Init Done");
}

/* ConfigTarget */
void ConfigTargetSettings(void)
{
Report("Config JTAG Speed to 4000kHz");
JTAG_Speed = 4000;
}

/* SetupTarget */
void SetupTarget(void) {
unsigned int reg;
reg = MEM_ReadU32(0x021B0000);
reg = reg & 0x80000000;

if(reg == 0){
Report("Enabling i.MX6ULL DDR3L");
Clock_Init();
DDR_Init();
}
}

 

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