K81 MCU in DryIce has a SR(Status Register).
SR Bit 7 (Security Tamper Flag) is set "when the (optional) security module asserts its tamper detect" according to the K81 User Manual.
"The SR[STF] bitfield description refers to an "(optional) security module". The 2KB
secure SRAM is the security module integrated into this device."
and according to a note in the UM: "A system reset causes STF to be set because the secure SRAM
detects a system reset as a tamper event."
Could anybody explain about the circumstances this flag is really set.
So far I've been working with K81 and monitoring various tamper flags but never managed to create a condition that would set STF.
Is it really active and linked to secure SRAM in the K81 MCUs ?