The SI32287 provides SPI and PCM interface to host. Also, the SPI interface pins SCLK, SPI_MOSI, SPI_MISO, & CHIP SELECT are mapped to Processors SPI port and the PCM interface pins MOSI, MISO, PCLK and frame Sync are mapped to the processor AudioMux port5(act as PCM).
The minimum PCLK frequency for PCM interface of SLIC IC should be 512KHz according to the datasheet. PCLK signal is mapped to TXC pin of AUDMUX Port 5 of processor.
Also, the PCLK frequency is dependent on the frame sync. My frame sync frequency is fixed of 8KHz.
Is the configuration possible for frame sync of 8KHz, Word-length of 64bits(for dual channel of SLIC) and PCLK of 512KHz?