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Question, i.MX8M Quad Lite power up sequence.

Question asked by Masamichi Miyamoto on Oct 21, 2018
Latest reply on Oct 24, 2018 by igorpadykov

Dear team,

 

I would like to ask about the power-up sequence of i.MX8M QL.

Please give your answers to the following questions.

 

1. Are there any time specific regulations on power-on or power-down sequence?

2. Is it possible for NVCC_XXX or NVCC_DRAM to rise up during VDDA_1P8_XXX or VDDA_DRAM are rising-up? Or should those (NVCC_XXX or NVCC_DRAM) rise-up after the completion of VDDA_1P8_XXX or VDDA_DRAM rising-up?

3. In your datasheet, it is said that the power supply of PHY should be ON after chip power up.

Please let me know the exact meaning of “power-up”.

 

Thanks,

Miyamoto

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