The S12ZVLA128 has 2 LIN buses. I am using SCI0 to drive the LIN Hardware Layer pin as a slave and SCI1 driving a LIN transceiver for the master bus. I have timer 0 chan 2 and SCI0 set up as software controlled interrupts in Processor Expert named correctly from what I found in the LIN driver code, and I had to perform VERY minor surgery to lin_isr.c to get it to play nicely with the ISR() formatting in Processor Expert. I also told PE that SCI0 and SCI1 will be manually configured.
When I run as a slave only everything works exactly as expected. As soon as I add a master bus and add the interrupt for SCI1 to PE it still compiles but the slave bus no longer recognizes incoming messages. I've placed a break point directly in the ISR routine and it is no longer breaking there.
There are no demos running both master and slave buses on the same micro. Has anyone run in to this?
Thanks in advance for any help.