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iMX 1052 LPSPI register behaviour

Question asked by Momchil Jeliazkov on Oct 19, 2018
Latest reply on Oct 23, 2018 by CarlosCasillas

Hi all, 


I'm using the LPSPI periphery in an rt1052 as a slave and have some issues with the register access.

Any reads I do from the TCR register are quite inconsistent. Here is some example code:



lpspi_slave_config_t slaveConfig;

slaveConfig.bitsPerFrame = 256;
slaveConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
slaveConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
slaveConfig.direction = kLPSPI_MsbFirst;
slaveConfig.whichPcs = kLPSPI_Pcs0;
slaveConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
slaveConfig.pinCfg = kLPSPI_SdiInSdoOut;
slaveConfig.dataOutConfig = kLpspiDataOutTristate;
LPSPI_SlaveInit(LPSPI_BASEADDR, &slaveConfig);

int err_reads = 0;
while (1)
uint32_t ph_tcr = LPSPI_BASEADDR->TCR;
if (ph_tcr==255)


This gets stuck forever in the while loop. If I add a " LPSPI_FlushFifo(LPSPI_BASEADDR, true, true);" before the 

TCR reads I seem to get more consistent behaviour and correct reads. This seems very weird to me as most of the provided drivers count on correct reading from the TCR and therefore don't work as expected, can you please clarify the correct access pattern for this register. I want to clarify that whatever I write in this register seems to be correctly applied, it is just that I cannot read it back correctly. 


I have a second issue with this periphery - I'm reading the rx fifo in a Receive data interrupt and every other transfer, while I'm reading the FIFO the "receive error flag" goes up. My transfers are 32bytes (8 words in the FIFO) and I trigger them manually from the master side so it is absolutely impossible that the fifo overruns - furthermore whenever I read the status register I read the FIFO status register right after that and I never encounter value higher than 8 in the RXCOUNT field. Interestingly, I receive the data correctly - all the values and all are correct, it just bothers me that this error flag goes up all the time, and I cannot understand if there is an actual error.