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Clarification of GPIO1 dedicated interrupts -- overlap with combination interrupt.

Question asked by Andrew DeAngelis on Oct 19, 2018
Latest reply on Oct 23, 2018 by igorpadykov

Hello. this is for a project with the IMX7D processor.


I have a question about the GPIO1[7:0] dedicated interrupts and the way they overlap with the shared GPIO1[15:0] interrupt -- Is it possible for an interrupt on GPIO[2] to show up on the dedicated interrupt but not trigger the combination interrupt? Say by masking that bit in the appropriate GPIO_IMR? Or will masking the pin in the IMR not only stop it from triggering the combo GPIO1[15:0] interrupt, but stop it from triggering the dedicated GPIO1[2] interrupt as well? Are the dedicated GPIO1[7:0] interrupts affected by the edge/level settings in the ICR registerm or do those only affect the shared GPIO1[15:0] interrupt?


Here is an illustrative situation. We have an interrupt on GPIO1[2] that should interrupt the A7 Core1, but not the A7 Core0. However there are interrupts on GPIO1[13:12] that must be serviced by A7 Core0. We don't want the ISR for shared GPIO1[15:0] running on A7 Core0 to be triggered by a GPIO2 falling edge, because it will happen very often, and even if the ISR is short, will affect performance. But, on a GPIO2 falling edge, we do want the A7 Core1 ISR for dedicated GPIO1[2] "Active HIGH INT2 from GPIO" interrupt to be run.


Does this change if A7Core 1 core was the M4 Core instead?


Thank you,