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i.MX6ULL Power-Up Sequence

Question asked by miki takashi on Oct 16, 2018
Latest reply on Oct 18, 2018 by miki takashi

Please tell us about the following points in Power-Up Sequence of i.MX6ULL.

 

1. IMX6ULLIEC.pdf (DataSheet) has no sequence description for the following power supply. Would you mind thinking that there is no sequence order if it is after VDD_SNVS_IN?
-NVCC_DRAM
-NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD
-VDDA_ADC_3P3,ADC_VREFH

 

2. Is there any problem with the POWER UP sequence(Step) below? Also, at Step 4, the NVCC (* 1) power supply is still OFF, but can not leak to the NVCC (* 1) power supply terminal (* 2)?
-Step1 : VDD_SNVS_IN (+3.3V)
-Step2 : VDD_HIGH_IN (+3.3V)
-Step3 : VDD_SOC_IN (+1.35V)
-Step4 : NVCC_DRAM (+1.35V)
-Step5 : NVCC(*1) / VDDA_ADC_3P3 / ADC_VREF(+3.3V)
(*1)NVCC : NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD

 

Thank you.

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