I am writing a routine for disabling an already enabled CPC. When I try to flush CPC during this course, set number 0 to 255 of the cache get flushed, but set number 256 to 511 do not get flushed.
I am using the method specified in P4080DS Reference Manual for disabling CPC:
a) Reset all CPCPARn registers
b) Set CPCFL in CPCCSR0 register
c) Wait for CPCFL to be reset by hardware
d) Clear locks by setting CPCLFC and wait for it to be reset by h/w.
e) Disable the CPC using CPCE bit.
Am I missing something or is there an errata related to this?