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K82 : cache and cache

Question asked by Eugene Hiihtaja on Oct 12, 2018
Latest reply on Oct 19, 2018 by Felipe Garcia

Hello !

 

1. In normal Cortex-M4  exists Auxiliary Control Register, ACTLR what user for enable/disable WriteBuffer.

#define CPU_REG_SCnSCB_ACTLR ( * (( uint32_t * )( 0xE000E008U )))
#define CPU_REG_SCnSCB_ACTLR_DISDEFWBUF ( 0x00000002U )

 

I think in case of K82 this WriteBuffer is missing because you have other set of caches -  LMEM.

And all functionality is implemented in fsl_cache.h/fsl_cache.c files.

 

In my design I using MPU module and interesting what is proper sequence to enable all caches ?

 

/*  SYSMPU Initialisation & Enable. */
SYSMPU_Init(SYSMPU, &userConfig1);

 

L1CACHE_EnableCodeCache();
L1CACHE_EnableCodeCacheWriteBuffer(true);
L1CACHE_EnableSystemCache();

 

Is this right order ?

 

2. Should I invalidate all caches and disable write buffer if I disable MPU  ?

 

3. Is any invalidation or temporary disabling are need if I put MCU to low power mode LLS3 ?

 

4. Do I undestand right, for achieve even better performance I should enable 

FTFx_CACHE_Init() as well ?

 

Should I set also FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t )

for enable prefech for code and data  ? Or it is enabled by default ?

 

When this cache should be enabled ? Before of after L1 caches ?

 

5. Is any other caches available on K82 to accelerate performance ?

 

6.  in SDK file fsl_ftfx_cache.c you have used a lot of code like this :

 

/* Memory barriers for good measure.
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
__ISB();
__DSB();

 

But why ISB executed before DSB ?

In all ARM documentation it is recommended other sequence:

 

__DSB()

__ISB()

 

Just interesting to know.

 

Regards,

Eugene

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