Does MMU for core-1 has default 4 KB page defined at 0x0_FFFF_Fnnn even when boot space translation is enabled? or Does MMU provides access for the page which is set it up by the Boot space translation register low (LCC_BSTRL)?
Can we set up TLB entry for the page defined in LCC_BSTRL for core-1 from core-0 before releasing the core-1?
I have referred u-boot code (mp.c), in that they are disabling the default reset page TLB and set it up that TLB with the page which will set up by LCC_BSTRL. Does default TLB entry is global for both cores?