AnsweredAssumed Answered

ADC using FIRC as system clock

Question asked by SUNIL KUMAR on Oct 11, 2018
Latest reply on Oct 16, 2018 by Diana Batrlova

I am trying to perform ADC Conversion with out using Processor Expert.

Below is the program which I have used.

When I execute the code, the program counter gets struck at the while(adc_complete()==0) check.

Which means, conversion is not happening.

Can anyone help me with a solution for this.

I guess, I am doing some mistake in the Clock initialization for ADC.

 

void main(void)

{

 

SlowRUNmode_FIRC_48MHz();
PORT_init(); /* Init ports */

ADC_init(); /* Init ADC resolution 12 bit*/

 

for(;;)

{
convertAdcChan(11); /* Convert Channel AD12 to pot on EVB */
while(adc_complete()==0){} /* Wait for conversion complete flag */
adcResultInMv_pot = read_adc_chx(); /* Get channel's conversion results in mv */

if ((adcResultInMv_pot >= 4650)&&(prechargedone == 0))
{PTE->PSOR |= 1<<PTE9;
}
convertAdcChan(29); /* Convert chan 29, Vrefsh */
while(adc_complete()==0){} /* Wait for conversion complete flag */
adcResultInMv_Vrefsh = read_adc_chx(); /* Get channel's conversion results in mv */

}

 

 

void SlowRUNmode_FIRC_48MHz(void)

{
SCG->RCCR=SCG_RCCR_SCS(3) /* FIRC as clock source*/
|SCG_RCCR_DIVCORE(0b00) /* DIVCORE=0, div. by 1: Core clock = 48/1 MHz = 48 MHz*/
|SCG_RCCR_DIVBUS(0b00) /* DIVBUS=0, div. by 1: bus clock = 24 MHz*/
|SCG_RCCR_DIVSLOW(0b01); /* DIVSLOW=1, div. by 2: SCG slow, flash clock= 26 2/3 MHz*/
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3) {}
/* Wait for sys clk src = FIRC */

}

 

void ADC_init(void) {
PCC->PCCn[PCC_ADC0_INDEX] &=~ PCC_PCCn_CGC_MASK; /* Disable clock to change PCS */
PCC->PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_PCS(0b011); /* PCS=0b11: Select FIRC */
PCC->PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable bus clock in ADC */

ADC0->SC1[0] =0x00001F; /* ADCH=1F: Module is disabled for conversions*/
                                             /* AIEN=0: Interrupts are disabled */
ADC0->CFG1 = 0x000000044;

ADC0->CFG2 = 0x0000000EF; 

ADC0->SC2 = 0x00000000; /* ADTRG=0: SW trigger */
                                             /* ACFE,ACFGT,ACREN=0: Compare func disabled */
                                             /* DMAEN=0: DMA disabled */
                                                /* REFSEL=0: Voltage reference pins= VREFH, VREEFL */
ADC0->SC3 = 0x00000000; /* CAL=0: Do not start calibration sequence */
                                                /* ADCO=0: One conversion performed */
                                                /* AVGE,AVGS=0: HW average function disabled */
}

 

void convertAdcChan(uint16_t adcChan)

{ /* For SW trigger mode, SC1[0] is used */
ADC0->SC1[0]&=~ADC_SC1_ADCH_MASK; /* Clear prior ADCH bits */
ADC0->SC1[0] = ADC_SC1_ADCH(adcChan); /* Initiate Conversion*/
}

 

uint8_t adc_complete(void)

{
return ((ADC0->SC1[0] & ADC_SC1_COCO_MASK)>>ADC_SC1_COCO_SHIFT); /* Wait for completion */
}

 

uint32_t read_adc_chx(void)

{
uint16_t adc_result=0;
adc_result=ADC0->R[0]; /* For SW trigger mode, R[0] is used */
return (uint32_t) ((5000*adc_result)/0xFFF); /* Convert result to mv for 0-5V range */
}

Outcomes