When the frequency of AHB and APB is 2M, the DMA sends 1024 word long data according to the sinusoidal code value of the table lookup. The refresh frequency of DAC is 1/6 of the set frequency.
If the frequency of sinusoidal code value is less than 100Hz, the output frequency is correct.At the same time, other parameters did not change, and APB only adjusted the corresponding divider coefficient after modifying the AHB clock to make the DAC output frequency unchanged, and the same sine wave code value, the output frequency was also increased synchronously. When AHB frequency was up to 32M, the frequency of DAC output was 2/3 of the set value.
I doubt that DMA cannot fully occupy the system bus bandwidth when actually transferring data, resulting in that the transmission bandwidth of actual DMA cannot meet the output rate requirements of DAC, and DAC cannot produce a corresponding output value under a single clock.
How to solve this problem?