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T1042 DDR ECC questions

Question asked by Kurt Ehrhardt on Oct 9, 2018
Latest reply on Oct 10, 2018 by ufedor

The T1040 RM (Sec 14.5.9) states that :

If a multi-bit error is detected for a read, the DDR memory controller logs the error and

generates the machine check or critical interrupt (if enabled, as described in Memory

error disable (DDR_ERR_DISABLE)).

 

We have a DDR double bit error injection test that corrupts mulitiple bits in a DDR word and reads back the word to force a DDR double bit error.  The MSR has machine check exceptions masked (MSR[ME] = 0) and (MSR[GS] = 0) i.e. not in guest state.  In addition DDR ERR_INT_EN=0 to disable all interrupts from single or multibit.  DDR_ERR_DISABLE=0 so all error detection is unmasked.  When the read of the corrupted word occurs an IVOR 1 machine check exception occurs, regardless of the MSR[ME]=0.  The MCSSR0 register contains the address of the instruction that reads back the corrupted word.  The MCSR contains 0xA000, uncorrectable L1 cache or tag error.  The MMU TLB1 entry for the DDR area is cache inhibitied and guarded (WIMGE bits=01010).  Why is the  machine check exception occuring if it is masked in the MSR and the ERR_INT_EN=0?

 

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