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Working with both MII and RGMII on iMX6 Solo X

Question asked by Alessandro Maggi on Oct 9, 2018
Latest reply on Oct 30, 2018 by Artur Petukhov

in our system we've connected an iMX6 Solo X to a Microchip KSZ8873FLLI switch using an MII interface at 100mbps.

For doing this, starting from the Sabre demo schematics, we've modified ENET1 connections to implement the MII physical layer.

ENET2 has been configured in RGMII mode and connected to a 100-FX PHY.

 

Actually, after the card power-on ENET2 is always working, while ENET1 sometimes is not.

Comparing TXD waveform to ENET2_TX_CLK, we've seen that the phase between data  and clock seems to change after each power-on.

Using SMI interface, we've verified that the KSZ8873 is always configured in a proper way.

 

Our main doubt is whether clock tree configuration is correct or not.

The clock tree is depicted in the attached block diagram.

ENET2_REF_CLK is used for providing the system clock to PHY and switch.

Referring to register IOMUXC_GPR_GPR1, our configuration is the following: 

ENET1_CLK_SEL = 0

ENET2_CLK_SEL = 0

ENET1_TX_CLK_DIR = 0

ENET2_TX_ CLK_DIR = 0

and IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK is set to ALT1.


Is this a correct setup for working with ENET1 in MII mode and ENET2 in RGMII mode?

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