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SEC Firmware enabled in LSDK 18.03 for LS1043ARDB

Question asked by Dan Lenz on Oct 7, 2018
Latest reply on Nov 30, 2018 by Pavel Chubakov

For version 18.03 of the LSDK I am seeing SEC Firmware being loaded in the uboot log. For versions 17.09 and 18.09 I do not see the entry in the log. Can you tell me how SEC firmware is enabled / disabled and why it is only showing up in 18.03? The SEC load works fine with 18.03 on the LS1043ARDB but when I run the same version on our custom board which uses the LS1023A it crashed uboot. Is the SEC firmware not compatible with the LS1023?

 

   SEC Firmware: 'loadables' present in config
   loadables: 'trustedOS@1'

 

U boot log from LSDK 18.03:

 

U-Boot SPL 2017.11-g00cde47 (Mar 22 2018 - 18:28:00)
Initialzing DDR using fixed setting
Configuring DDR for 1600 MT/s data rate
Trying to boot from MMC1
mmc_init: -110, time 746
spl: mmc init failed with error: -110
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

U-Boot SPL 2017.11-g00cde47 (Mar 22 2018 - 18:28:00)
Initialzing DDR using fixed setting
Configuring DDR for 1600 MT/s data rate
Trying to boot from MMC1


U-Boot 2017.11-g00cde47 (Mar 22 2018 - 18:28:00 +0800)

SoC: unknown (0x87920411)
Clock Configuration:
CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz
CPU3(A53):1600 MHz
Bus: 400 MHz DDR: 1600 MT/s FMAN: 500 MHz
Reset Configuration Word (RCW):
00000000: 08100010 0a000000 00000000 00000000
00000010: 14550002 80004012 60040000 c1002000
00000020: 00000000 00000000 00000000 00038800
00000030: 00000000 00001100 00000096 00000001
Model: LS1043A RDB Board
Board: LS1043ARDB, boot from SD
CPLD: V1.5
PCBA: V3.0
SERDES Reference Clocks:
SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ
I2C: ready
DRAM: 1.9 GiB (DDR4, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 5205 (0x1455)
SEC0: RNG instantiated
FSL_SDHC: 0
PPA Firmware: Version LSDK-18.03
SEC Firmware: 'loadables' present in config
loadables: 'trustedOS@1'

MMC read: dev # 0, block # 18952, count 128 ...
Not a microcode
Flash: 128 MiB
NAND: 512 MiB
MMC: *** Warning - bad CRC, using default environment

 

 

U boot log from 17.09:

 

U-Boot SPL 2017.07-g503eff0 (Sep 26 2017 - 15:01:33)
Initializing DDR....
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Trying to boot from MMC1


U-Boot 2017.07-g503eff0 (Sep 26 2017 - 15:01:33 +0800)

SoC: unknown (0x87920411)
Clock Configuration:
CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz
CPU3(A53):1600 MHz
Bus: 400 MHz DDR: 1600 MT/s FMAN: 500 MHz
Reset Configuration Word (RCW):
00000000: 08100010 0a000000 00000000 00000000
00000010: 14550002 80004012 60040000 c1002000
00000020: 00000000 00000000 00000000 00038800
00000030: 00000000 00001100 00000096 00000001
Model: LS1043A RDB Board
Board: LS1043ARDB, boot from SD
CPLD: V1.5
PCBA: V3.0
SERDES Reference Clocks:
SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ
I2C: ready
DRAM: Detected UDIMM Fixed DDR on board
1.9 GiB (DDR4, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 5205 (0x1455)
SEC0: RNG instantiated
FSL_SDHC: 0
PPA Firmware: Version LSDK-17.09

MMC read: dev # 0, block # 18952, count 128 ...
Not a microcode
Flash: 128 MiB
NAND: 512 MiB

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