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Where to make uboot and kernel changes to enable ecc_fix_en?

Question asked by Tracy Smith on Oct 4, 2018
Latest reply on Oct 12, 2018 by Tracy Smith

LS1043ARMv3 IFC has corrupted data disable reg 0x1080114 bit 30. If this bit is set then the corrupted data feature is disabled. When the corrupted data feature is enabled, the DDR controller will invert the generated ECC code for any beat of data which is known to have corrupted data. When a read to the corrupted data is later generated, the ERR_DETECT[CDE] error will be set if error reporting is enabled another field is DDR_SDRAM_CFG_3 1080260. ecc_fix_en is bit 1 and ecc_scrub_int is bit 4-7.  NXP has never enable this feature in the development boards because of the potential performance impact on memory. But I need to do periodic scrubbing and ECC error correction and will need to enable this feature of the IFC.

 

1) Where do I modify the code and what code changes are needed in the Linux kernel and uboot to enable ecc_fix_en and ecc_scrub_int?

 

2) For example, I see the following ddr_cfg_regs_1600.  Anything similar for the kernel and uboot source for the ls1043 ecc supported platforms?

 

3) I don't see this code in the fsl lsdk source available for download, will the code below be in the next release of the lsdk?

 

4) Is this from the most recent lsdk changes for the uboot ddr?

 

 https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/board/freescale/ls1043ardb/ddr.h?h=v2018.09

 

#ifndef CONFIG_SYS_DDR_RAW_TIMING

fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {

        .cs[0].bnds = 0x0000007F,

        .cs[1].bnds = 0,

        .cs[2].bnds = 0,

        .cs[3].bnds = 0,

        .cs[0].config = 0x80040322,

        .cs[0].config_2 = 0,

        .cs[1].config = 0,

        .cs[1].config_2 = 0,

        .cs[2].config = 0,

        .cs[3].config = 0,

        .timing_cfg_3 = 0x010C1000,

        .timing_cfg_0 = 0x91550018,

        .timing_cfg_1 = 0xBBB48C42,

        .timing_cfg_2 = 0x0048C111,

        .ddr_sdram_cfg = 0xC50C0008,

        .ddr_sdram_cfg_2 = 0x00401100,

        .ddr_sdram_cfg_3 = 0,

        .ddr_sdram_mode = 0x03010210,

        .ddr_sdram_mode_2 = 0,

        .ddr_sdram_mode_3 = 0x00010210,

        .ddr_sdram_mode_4 = 0,

        .ddr_sdram_mode_5 = 0x00010210,

        .ddr_sdram_mode_6 = 0,

        .ddr_sdram_mode_7 = 0x00010210,

        .ddr_sdram_mode_8 = 0,

        .ddr_sdram_mode_9 = 0x00000500,

        .ddr_sdram_mode_10 = 0x04000000,

        .ddr_sdram_mode_11 = 0x00000400,

        .ddr_sdram_mode_12 = 0x04000000,

        .ddr_sdram_mode_13 = 0x00000400,

        .ddr_sdram_mode_14 = 0x04000000,

        .ddr_sdram_mode_15 = 0x00000400,

        .ddr_sdram_mode_16 = 0x04000000,

        .ddr_sdram_interval = 0x18600618,

        .ddr_data_init = 0xDEADBEEF,

        .ddr_sdram_clk_cntl = 0x03000000,

        .ddr_init_addr = 0,

        .ddr_init_ext_addr = 0,

        .timing_cfg_4 = 0x00000002,

        .timing_cfg_5 = 0x03401400,

        .timing_cfg_6 = 0,

        .timing_cfg_7 = 0x13300000,

        .timing_cfg_8 = 0x02115600,

        .timing_cfg_9 = 0,

        .ddr_zq_cntl = 0x8A090705,

        .ddr_wrlvl_cntl = 0x8675F607,

        .ddr_wrlvl_cntl_2 = 0x07090800,

        .ddr_wrlvl_cntl_3 = 0,

        .ddr_sr_cntr = 0,

        .ddr_sdram_rcw_1 = 0,

        .ddr_sdram_rcw_2 = 0,

        .ddr_cdr1 = 0x80040000,

        .ddr_cdr2 = 0x0000A181,

        .dq_map_0 = 0,

        .dq_map_1 = 0,

        .dq_map_2 = 0,

        .dq_map_3 = 0,

        .debug[28] = 0x00700046,

 

};

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