Maximum external memory size to support by Solo X

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Maximum external memory size to support by Solo X

Jump to solution
664 Views
takayuki_ishii
Contributor IV

Hello community,

I have some basic questions about i.MX6SoloX DDR and EIM.

    1) maximum memory size of DDR.

        - In MMDC it can allocate 4GByte (32bit address). It can mapped 2GByte area selected from 4GByte physical memory area for Cortex-A9 and 1.5GByte for Cortex-M4.

    Is it correct?

    2) maximum memory size of NOR-Flash.

        - In i.MX6Solo, it have EIM errata ERR004446 "EIM: AUS mode is nonfunctional for devices larger than 32 MB"

          In i.MX6SoloX this errata is fixed in EIM rev2. So A24 can work correctly and it can map more than 32MByte parallel  NOR-Flash.

    Is it correct?

    3) In DSZ bit Description of EIM_CSnGCR1 register, "NOTE:" say as following.

        "NOTE: Only async. access supported for 8 bit port."

    It say that 8bit port mode can use with only async setting.

    It doesn't say that async mode is not support 16/32bit port access.

    Is it correct?

I look forward to hearing from you.

Best regards,

Ishii.

Labels (1)
0 Kudos
1 Solution
534 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

1. msx.size is given in Table 2-1. System memory map i.MX6SX Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

2GB for Cortex-A9 and 1.5GB for Cortex-M4

2. 128MB according to the same table

3. correct

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
4 Replies
535 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

1. msx.size is given in Table 2-1. System memory map i.MX6SX Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

2GB for Cortex-A9 and 1.5GB for Cortex-M4

2. 128MB according to the same table

3. correct

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
534 Views
takayuki_ishii
Contributor IV

Hello Igor,

Thank you for your quick response.

1. msx.size is given in Table 2-1. System memory map i.MX6SX Reference Manual 
http://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

2GB for Cortex-A9 and 1.5GB for Cortex-M4

In section 40.4.4.2 Chip select settings of IMX6SXRM and 

3.5 Routing considerations of IMX6SXHDG say that it can create 4 GBytes address space and

allocate 2 GBytes(CA9) from 4 GBytes address space.

Is it not recommended to use 4 GBytes DRAM?

2. 128MB according to the same table

OK. I understand that A24 not function problem will improved.

3. correct

OK. I will answer it to my customer.

Best regards,

Ishii.

0 Kudos
534 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

>Is it not recommended to use 4 GBytes DRAM?

right

Best regards
igor

0 Kudos
534 Views
takayuki_ishii
Contributor IV

Hell Igor,

Thank you for your quick response.

I understand it.

Best regards,

Ishii.

0 Kudos