Why doesn't use PCIE Gen 1 recommendation in Freescale SabreSD board ?

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Why doesn't use PCIE Gen 1 recommendation in Freescale SabreSD board ?

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peteramond
Contributor V

Hi All,

When I go through in Hardware design check list I could see following.

pastedImage_3.png

But when we refer Freescale Sabre SD board we can't see those changes. It should be both 470 Ohms and 56 Ohms pull up and pull down resistors for PCIE REFCLK.

In Freescale SabreSD board

pastedImage_1.png

In NXP iMAX6Q hardware design checklist.

pastedImage_2.png

1) Could you please explain why freescale is not using those changes ?

2) Why we need to use LVDS port for PCIE clock ? Is this a fault from NXP ? Any possibility to don't work or not getting stable PCIE link even without using recommended hardware settings (Pull up and pull down) ?

3) Why we use both pull up and pull down ?

Regards,

Peter

3 Replies

527 Views
igorpadykov
NXP Employee
NXP Employee

Hi Peter

>1) Could you please explain why freescale is not using those changes ?

reason is that Sabre board was developed in early development stage when not
all compliance tests were carried out.

>2) Why we need to use LVDS port for PCIE clock ? Is this a fault from NXP ?

PCIe module is gen2 compliant block but the clock is not coming out of this module.

>3) Why we use both pull up and pull down ?

seems this sets some voltage level which complies with sect.4.3.4.4. Receiver Specifications
PCI-Express base specification found on Specifications | PCI-SIG 

Best regards
igor
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527 Views
peteramond
Contributor V

igorpadykov

Hi igor,

 

Thank you for your feedback. I can't get

"sect.4.3.4.4. Receiver Specifications PCI-Express base specification found on Specifications | PCI-"

 

above link need to register for that. Could you please tell me what is that saying ?

 

Regards,

Peter.

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527 Views
igorpadykov
NXP Employee
NXP Employee

Hi Peter

unfortunately documents are available only for members of PCI-SIG

association. In other words pull up and pull down set some voltage

within allowable range, defined by Table 4. Absolute Maximum Ratings

for Vin/Vout input/output voltage range i.MX6DQ Datasheet

and sect.4.3.4.4. Receiver Specification PCI-Express base specification.

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf 

Best regards
igor

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