For any layerscape product where ECC is enabled (e.g. LS1043A-QDS, LS1046A-RDB) how and specifically where are DDR_SDRAM_CFG_2[D_INIT]=0b'1 and DDR_SDRAM_CFG[ECC_EN]=0b'1 configured in the Linux kernel? Not asking where they are enabled in uboot.
If they are only configured in uboot on the LS1043A-QDS, why?
You wrote:
> If they are only configured in uboot on the LS1043A-QDS, why?
Please consider that basic ECC SDRAM double-word consists of 8 data bytes and 1 ECC byte.
For normal ECC SDRAM operation in each double-word ECC byte value must correspond to its data bytes vlaues.
This correspondence can not be established when code is executed from SDRAM (in this case DDR controller will detect ECC errors) - this is why the ECC SDRAM is explicitly initialized in hardware (by means of the DDR controller) even before the U-Boot code is relocated to SDRAM.
I don’t understand. Are you saying I cannot write to the ECC registers using devmem because there is one extra ECC byte that cannot be written to even though the four ECC lines are connected?
if so, why is that the case? I should be able to write to these bits on the LS1043AQDS without the board resetting.