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Accessing on PCIe memory

Question asked by utkarsh rawat on Oct 3, 2018

Hi All 

I want to communicate T1042 processor with AXI fpga through pcie. I can able to access AXI fpga configuration details that are listed below

-> vendor ID =                   0x10ee

device ID =                   0x7022

command register =            0x0007

status register =             0x0010

revision ID =                 0x00

class code =                  0x05

sub class code =              0x80

programming interface =       0x00

cache line =                  0x10

latency time =                0x00

header type =                 0x00

BIST =                        0x00

base address 0 =              0xa0000000

base address 1 =              0x00000000

base address 2 =              0x00000000

base address 3 =              0x00000000

base address 4 =              0x00000000

base address 5 =              0x00000000

cardBus CIS pointer =         0x00000000

sub system vendor ID =        0x10ee

sub system ID =               0x0007

expansion ROM base address =  0x00000000

interrupt line =              0x29

interrupt pin =               0x01

min Grant =                   0x00

max Latency =                 0x00

Capabilities - Power Management

Capabilities - Message Signaled Interrupts: 0x48 control 0x80

 

But when I am writing onto the address 0xa000_0000 on the fpga side ,i am not able to access the data. 

Code is below

#define PCI_BAR0 0xA0000000

 

fpga_Write(0x0000,0x2222);

 

int fpga_Write(unsigned int Addr,unsigned long data){
*(unsigned int *)(PCI_BAR0+Addr) = data;
return 0;
}

Device tree configuration is below 

pci1: pcie@ffe250000 {
compatible = "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
interrupts = <21 2 0 0>;
#interrupt-cells = <1>;
reg = <0xf 0xfe250000 0 0x10000>;
/*
* EEEEEEEEEE address properties encoded
* p PCI address upper 32 bits
* PPPPPPPPPP PCI address lower 32 bits
* ccc CPU address upper 32 bits
* CCCCCCCCCC CPU address lower 32 bits
* s range size upper 32 bits
* SSSSSSSSSS range size lower 32 bits
*
* EEEEEEEEEE p PPPPPPPPPP ccc CCCCCCCCCC s SSSSSSSSSS
*/
ranges = <0x02000000 0 0xa0000000 0xf 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
interrupt-map-mask = <0xfff800 0 0 7>;
interrupt-map = <
0000 0 0 1 &mpic 41 1 0 0
0000 0 0 2 &mpic 5 1 0 0
0000 0 0 3 &mpic 6 1 0 0
0000 0 0 4 &mpic 7 1 0 0
>;
};

I have few question that are highlighted below 

 

1. Do I need to send data though TLP layer. How should I do that

2. Checked PCI Express memory-mapped registers .Under that enable these registers 

         2.1 PCI Express configuration address register

         2.2 PCI Express configuration data register

but not sure on which address need to write on ,since  I am using pci2 controller 2 ,i am writing on 0x25_0000 or do I have to write on 0xffe250000 (highlighted in DTS configuration)

 

Thanks 

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