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Inter core communication

Question asked by Ken Green on Sep 27, 2018
Latest reply on Oct 25, 2018 by Ken Green

I'm using a Vybrid processor (A5 + M4). I need to pass data from the M4 to the A5 core in DDR memory. I can't simply write to a memory space using the M4 and have the A5 read the same space because the A5 data is cached. The A5 would know nothing about the new data. Is there a way to accomplish this?